ESTIMATING FUTURE CARDS TRANSISTOR COUNT – FOR GEFORCE 8XX SERIES

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Im going to estimate, using simple math based on unit analysis, how many transistors the future cards will have. The ones coming out with the 20 nm process as promised. Like the Geforce 890 or Geforece 870 etc. These are all estimates, I bet I will come close.

Also its interesting to see typical Laptop graphics chip the INTEL HD 4000 for example has a smaller process then the GPU (because intel uses the smaller process size in their fabs) and yet of course INTELs efficeincy shoving Transistors onto a die is not as good. No offense INTEL – I Love you and all but NVIDIAs got the upper hand on transistors on their GPUs at least.

My conclusions are the bottom

My Math:

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WARNING EXTREMELY SIMPLE

Given: Die Size [Area units], Process Size [Length units], Transistor Count[no units]

# of Grids = Die Size / (Process ^ 2)

Grids Per Transistor = # of Grids / Transistor Count

Thus:

Transistor Count = # of Grids * Grids Per Transistor

Transistor Count = (Die Size / (Process * Process)) /  Grids per Transistors

MY CARD GEFORCE 670

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Die size: 294mm^2

Process Size: 28nm

Transistors: 3540000000 transistors

Grids: (294 (mm^2)) / ((28 nm)^2) = 375 000 000 000  grids  ***

Grids per Transistor: ((294 (mm^2)) / 3 540 000 000) / ((28 nm)^2) = 105.932203  little blocks per transistor

GEFORCE 690

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Process Size: 28nm

Transistors: 3.54bn x 2

Die Size: 294mm² x 2

690 per single die

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Die size: 294mm^2

Process Size: 28nm

Transistors: 3540000000 transistors

Grids: (294 (mm^2)) / ((28 nm)^2) = 375 000 000 000  grids ***

Grids per Transistors: ((294 (mm^2)) / 3 540 000 000) / ((28 nm)^2) = 105.932203  little blocks per transistor ***

GEFORCE TITAN

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Transistors: 7100000000 transistors

Die size: 294mm 550mm^2

Process: 28nm

Grids: (550 mm^2) / ((28 nm)^2) =  7.01530612 × 10^11    grids ***

Grids Per Transistor: ((550 mm^2) / 7100000000) / ((28 nm)^2 = 98.8071285  little blocks per transistor

R290X

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Die Size: 438 mm ^2

Transistors: 6200000000

Grids: (438 (mm^2)) / ((28 nm)^2) = 5.58673469 × 10^11   grids ***

Grids Per Transistors: ((438 mm^2) / 6200000000) / ((28 nm)^2 = 90  little blocks per transistor ***

INTERESTING – CRAPPY LENOVO EMBEDDED CARD – INTEL HD GRAPHICS 4000

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I was surprised to see their process is smaller (of course they use the intel fabs) 22 nm 🙂 Anyhow they are less efficeint at transistor placement, check out the math to see:

Installed Z-GPU 0.7.5 to get this from my Lenovo Work Laptop

INTEL HD GRAPHICS 4000

Much less efficient @ transistor placement.

CONCLUSION FROM GIVEN CURRENT CARDS:

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About 100 Grids boxes per Transistor. A Grid box is just as big as the PRocess Size Box (Process by Process Long)

ESTIMATING FUTURE CARDS WITH 20 nm PROCESS

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***Simple Math***

Die Size / (Process * Process) = Grids

Transistors = Grids / Grids per Transistors = Grids / 100

Transistors = (Die Size / (Process * Process)) /  Grids per Transistors

Transistors = (Die Size / (Process * Process)) / 100

We know Grids Per Transistors is the same size.

Im assuming Die sizes will remain the same.

DIE SIZE 20 nm

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294 mm^2, process: 20nm = GRIDS: 735 000 000 000 – TRANSISTORS: 13,750,000,000 – 13.8 billion **

294 mm^2 X 2, process: 20nm = GRIDS: 735 000 000 000 X2 – TRANSISTORS: 27,500,000,000 – 27.5 billion **

438 mm^2, process: 20nm =  1 095 000 000 000 – TRANSISTORS: 10,950,000,000 – 11.0 billion **

550 mm^2, process: 20nm =  1 375 000 000 000 – TRANSISTORS: 13,750,000,000 – 13.8 billion **

CONCLUSIONS

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Die Size and Transistor conclusion:

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294 mm^2 => 13.8 billion  Transistors

294 mm^2 X 2 => 27.5 billion Transistors

438 mm^2 => 11.0 billion Transistors

550 mm^2 => 13.8 billion Transistors

My estimate @ Transistor count

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890 – 27.5 billion ( A card with 2 dies of die size of 294 mm^2 each )

870 – 13.8 billion  ( A card with 2 dies of die size of 294 mm^2 each )

The rest are above